The processes involved in the manufacture of a semiconductor circuit substrate include, among others, layering, patterning, doping and heat treatment. One type of heat treatment concerns the use of heat to alloy conductor lines (e.g., form contacts) to a wafer surface. This type of heat treatment may take place in a nitrogen gas atmosphere. Annealing is another type of heat treatment.
Annealing, in one aspect, cures defects caused in a crystal wafer (e.g., crystal semiconductor wafer) structure during the introduction of dopant. One method of introducing dopant is ion implantation. In ion implantation, a wafer is bombarded with ion energy. As ions enter the wafer, the ions collide with atoms in the crystal wafer structure, thus causing defects in the crystal wafer structure. These defects may degrade semiconductor characteristics such as mobility. Annealing may be used to recrystallize wafer material and to minimize crystal defects. In another aspect, annealing may be used to activate dopants.
If annealing is performed in a tube furnace, heat is typically applied at a temperature between 600 and 1000 C. Annealing in a tube furnace may be performed in a hydrogen atmosphere. Rapid Thermal Annealing (RTA) and Rapid Thermal Processing (RTP) are two other processes used to heat surfaces of semiconductor devices. These processes involve directing light at a semiconductor surface for a relatively long duration (e.g., from tenths of a second to multiple seconds). Laser annealing is another process used to heat surfaces. Present state of the art laser annealing commonly uses pulses lasting tens of nanoseconds resulting in uneven heating of surfaces with topography or topology. In RTP, anneal may be performed in seconds, while tube process annealing may require a heat treatment extending from 15 to 30 minutes. The long anneal times required by such processes can result in thermal diffusion. Specifically, following the introduction of dopant, when a host material is heated, dopant may diffuse laterally or vertically, and may therefore hinder efforts to form, for example, an abrupt P-N junction.
Additionally, processes like RTP result in uneven heating of various surface points on a semiconductor or substrate surface that have varying topographies or topologies. For example, the topography of a semiconductor device may vary across the surface of the device. A surface point on top of a substrate, in an area between two gates, may be in a lower relative vertical position than a surface point which is on top of a polysilicon line. Because the topography differs among these surface points, prior art methods of heating semiconductor devices may result in uneven heating among these surface points. Specifically, those surface points that have a higher vertical position may be over-heated, in comparison to surface points having a lower vertical position. Over-heating may result in the softening of surface materials and/or sub-surface materials. Softening may lead to deformation of the semiconductor device surface, and may prevent or reduce the capacity to form abrupt junctions on the semiconductor device.
Just as topography differs among surface points, topology may also differ among surface points. In this regard, a substrate may include sections having different optical, chemical and/or electrical properties. For example, a substrate may include a silicon section, a P-N junction, and an oxide isolation area. Surface points on top of these materials may have a similar topography, but the topology differs, which affects how the surface points react to heat. Specifically, those surface points in respect of which the surface materials and/or sub-surface materials have relatively lower melting points may be over-heated, in comparison to surface points having a relatively higher melting point. Differences in the thermal conductivity of various materials can also result in an uneven heating of the surfaces. Over-heating may result in the softening of surface material and sub-surface materials. Softening may lead to deformation of the semiconductor device surface, and may prevent or reduce the capacity to produce abrupt junctions in the semiconductor device.